1. Field of the Invention
This invention is related to the field of processors and, more particularly, to micro coding in processors.
2. Description of the Related Art
Processor designers often design their products in accordance with the x86 instruction set architecture (ISA) in order to take advantage of its widespread acceptance in the computer industry. Because the x86 ISA is pervasive, many computer programs are written in accordance with the architecture. X86 compatible processors may execute these computer programs, thereby becoming more attractive to computer system designers who desire x86-capable computer systems. Such computer systems are often well received within the industry due to the wide range of available computer programs.
Certain instructions within the x86 instruction set are quite complex, specifying multiple operations to be performed. For example, the PUSHA instruction specifies that each of the x86 registers be pushed onto a stack defined by the value in the ESP register. The corresponding operations are a store operation for each register, and decrements of the ESP register between each store operation to generate the address for the next store operation. Often, complex instructions are classified as microcode instructions (or MROM instructions, for microcode read-only memory). MROM instructions are transmitted to a microcode unit, or MROM unit, within the processor. The MROM instruction is implemented as a microcode routine or routines stored in a memory within the MROM unit, where the microcode routine comprises simpler microcode operations for execution by the processor. The microcode routines are typically stored in a read-only memory (ROM) within the microcode unit. The microcode unit determines an address within the ROM at which the routine begins, and the microcode unit transfers operations out of the ROM beginning at that address. The microcode routines can include loops, one or more iterations of which can be executed to complete an MROM instruction.
Conversely, less complex instructions are decoded by hardware decode units within the processor, without intervention by the microcode unit. The terms “directly-decoded instruction” and “fastpath instruction” will be used herein to refer to instructions which are decoded and executed by the processor without the aid of a microcode unit. As opposed to MROM instructions which are reduced to simpler instructions which may be handled by the processor, fastpath instructions are decoded and executed via hardware decode and functional units included within the processor. While the x86 ISA is used as an example of an ISA that may be implemented using at least some microcoding, other ISAs may be implemented using micro coding as well.